A multiplexer generally selects one of multiple input signals in response to one or more control signals and outputs the selected signal. In one application, multiplexers are used in the programmable signal routing structure of programmable logic devices (PLDs). These multiplexers may be referred to as interconnect multiplexers. The interconnect multiplexers are programmed based on a particular design having been synthesized, mapped, placed, and routed. For a PLD circuit design, a configuration bitstream is generated from the placed-and-routed design data. The configuration bitstream programs each interconnect multiplexer according to the required routing.
Various programmable resources of a PLD may be unused by an implemented design, resulting in some of the logic pins in a PLD being unused. One PLD implementation requires these unused logic pins to be driven with a logic high signal. The signal that drives an unused logic pin with a logic high signal is provided by one of the interconnect multiplexers, which is programmed to always output a logic high signal.
Two example approaches have been used to make an interconnect multiplexer programmable to always output a logic high signal. In one approach, one of the input pins of the interconnect multiplexer is tied to the power supply voltage and the interconnect multiplexer is programmable to always select that input pin. This approach reduces the available connectivity of the interconnect multiplexer because one of the input pins is always tied to the power supply voltage regardless of whether the interconnect multiplexer is programmed to route a signal of the design or is programmed to provide the logic high signal to an unused logic pin.
Another approach is to force an internal node of the interconnect multiplexer to logic high with a power-on reset signal, and further rely on a half-latch to hold the node at logic high. With the half-latch approach, it may be difficult for silicon verification (product and test engineering) to test whether or not the half-latch is functioning properly. In addition, there may be scenarios in which the PLD is partially reconfigured and the state of the half-latch cannot be guaranteed to be logic high. Also, there is no apparent manner to detect if the half-latch is flipped to logic low.
The present invention may address one or more of the above issues.